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MPC8540 bảng dữ liệu(PDF) 309 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8540
Giải thích chi tiết về linh kiện  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8540 bảng dữ liệu(HTML) 309 Page - Freescale Semiconductor, Inc

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Cache Organization
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
7-5
Figure 7-4. 128-Kbyte L2 Cache Address Configuration—Half SRAM, Half
Cache Mode
The e500 core connects to the L2 cache and the system interface through the high-speed core
complex bus (CCB). The e500 core and the L2 cache connect to the rest of the integrated device
through the e500 coherency module (ECM). Figure 7-5 shows the data connections of the e500
core and L2/SRAM. The e500 core can simultaneously read 128 bits of data from the L2/SRAM,
read 64 bits of data from the system interface, and write 128 bits of data to the L2/SRAM and/or
system interface.
The L2/SRAM can be accessed by the e500 core or the system interface through the ECM. The L2
cache does not initiate transactions. Figure 7-5 shows the data bus connections of the e500 core
and L2/SRAM.
.
Figure 7-5. Data Bus Connection of CCB
31
27
26
Byte Select
Set Index
(9 bits)
18
(within a cache line)
(5 bits)
26
18
17
0
Tag (18 bits)
Way Select (SRAM access only)
(3 bits)
Tag Lookup
Data Read/Write
15
17
Set Index
(9 bits)
e500 Core
L2/SRAM
WR
RD2
DOUT WR IN
RD1
RD IN
64
e500 Coherency Module
128
128
(ECM)



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