MPC8540 datasheet(308/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-4

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

The tag size depends on whether both 128-Kbyte arrays are configured as cache. Figure 7-3 shows

how physical address bits are used to access the L2 in full cache mode (256-Kbyte cache).

Figure 7-3. 256-Kbyte L2 Cache Address Configuration—Full Cache Mode

Physical address bits 17–26 identify the bank and set of the tag and data. Physical address bits

0–16 are compared against the tags of all 8 ways. A match of a valid tag selects a 32-byte block of

data within the set. Physical address bits 27–31 identify the byte or bytes of data within the block.

If the L2 is programmed as one block of 256-Kbyte SRAM, physical address bits 14–16 are used

as the way select, without a tag lookup.

In half SRAM, half cache mode (128-Kbyte cache), there is no bank select, as shown in Figure 7-4,

so the tag is 18 bits (with no parity bit) for cache accesses. The cache resides in bank 1, and the

SRAM in bank 0. For SRAM accesses, physical address bits 15–17 are used as the way select. If

the L2 is programmed as two blocks of 128-Kbyte SRAM, bank 0 is block 0 (defined by

L2SRBAR0, see Table 7-5) and bank 1 is block 1.

As shown in Figure 7-4, the tag is 18 bits (with no parity bit) for cache accesses. For SRAM

accesses, physical address bits 15–17 are used as the way select.

Set index

(9 bits)

Bank select

Tag (17 bits)

Byte select

Set index

(9 bits)

Bank select

(5 bits)

(within a cache line)

Tag Lookup

Data Read/Write

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