MPC8540 datasheet(298/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-48

Freescale Semiconductor

Core Register Summary

6.13.4 Data Address Compare Registers (DAC1–DAC2)

6.14 Signal Processing and Embedded Floating-Point Status and

Control Register (SPEFSCR)

Field

Data address

Reset

All zeros

R/W

SPR

SPR 316 (DAC1); SPR 317 (DAC2)

Figure 6-53. Data Address Compare Registers (DAC1–DAC2)

Field SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH

—

FINXS FINVS FDBZS FUNFS FOVFS MODE

Reset

0000_0000_0000_0000

R/W

Field SOV

FINV

FDBZ

FUNF

FOVF — FINXE FINVE FDBZE FUNFE FOVFE

FRMC

Reset

0000_0000_0000_0000

R/W

SPR

SPR 512

Figure 6-54. Signal Processing and Embedded Floating-Point Status and Control

Table 6-36. SPEFSCR Field Descriptions

Bits

Name

Function

SOVH

Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH

remains set until it is cleared by an mtspr[SPEFSCR].

OVH

Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE

integer instruction

FGH

Embedded floating-point guard bit high. Floating-point guard bit from the upper half. The value is

undefined if the processor takes a floating-point exception due to input error, floating-point overflow,

or floating-point underflow.

FXH

Embedded floating-point sticky bit high. Floating bit from the upper half. The value is undefined if the

processor takes a floating-point exception due to input error, floating-point overflow, or floating-point

underflow.

High-Word Error Bits

Status Bits

Enable Bits

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