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MPC8540 bảng dữ liệu(PDF) 286 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
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MPC8540 bảng dữ liệu(HTML) 286 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
6-36
Freescale Semiconductor
Core Register Summary
6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)
Table 6-24. TLB0CFG Field Descriptions
Bits
Name
Description
32–39
ASSOC
Associativity of TLB0
0x02 indicates associativity is 2-way set associative
40–43
MINSIZE
Minimum page size of TLB0
0x1 indicates smallest page size is 4K
44–47
MAXSIZE Maximum page size of TLB0
0x1 indicates maximum page size is 4K
48
IPROT
Invalidate protect capability of TLB0
0 Indicates invalidate protection capability not supported
49
AVAIL
Page size availability of TLB0
0 No variable-sized pages available (MINSIZE = MAXSIZE)
50–51
—
Reserved, should be cleared.
52–63
NENTRY
Number of entries in TLB0
0x100: TLB0 contains 256 entries
32
39 40
43 44
47
48
49
50 51 52
63
Field
ASSOC
MINSIZE
MAXSIZE IPROT AVAIL
—
NENTRY
e500 Reset Values
0001_0000
0001
1001
1
1
00
0000_0001_0000
R/W
Read only
SPR
SPR 689
Figure 6-41. TLB Configuration Register 1 (TLB1CFG)
Table 6-25. TLB1CFG Field Descriptions
Bits
Name
Description
32–39
ASSOC
Associativity of TLB1
0x10 indicates associativity is 16
40–43
MINSIZE
Minimum page size of TLB1
0x1 indicates smallest page size is 4K
44–47
MAXSIZE Maximum page size of TLB1
0x9 Indicates maximum page size is 256 Mbyte
48
IPROT
Invalidate protect capability of TLB1
1 Indicates that TLB1 supports invalidate protection capability
49
AVAIL
Page size availability of TLB1
1 Indicates all page sizes between MINSIZE and MAXSIZE supported



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