MPC8540 datasheet(285/1302 Pages) FREESCALE

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MMU Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-35

6.12.3 MMU Configuration Register (MMUCFG)

6.12.4 TLB Configuration Registers (TLBnCFG)

6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG)

48 49

52 53

57 58 59

Field

—

NPIDS

PIDSIZE

—

NTLBS MAVN

Reset

0000_0000_0000_0000_0

001_1

001_11

R/W

Read only

SPR

SPR 1015

Figure 6-39. MMU Configuration Register (MMUCFG)

Table 6-23. MMUCFG Field Descriptions

Bits

Name

Description

32–48

—

Reserved, should be cleared.

49–52

NPIDS

Number of PID registers, a 4-bit field that indicates the number of PID registers provided by the

processor. The e500 implements three PIDs.

53–57

PIDSIZE PID register size. The 5-bit value of PIDSIZE is one less than the number of bits in each of the PID

registers implemented by the processor. The processor implements only the least significant

PIDSIZE+1 bits in the PID registers.

00111 indicates 8-bit registers. This is the value presented by the e500.

58–59

—

Reserved, should be cleared.

60–61

NTLBS

Number of TLBs. The value of NTLBS is one less than the number of software-accessible TLB

structures that are implemented by the processor. NTLBS is set to one less than the number of

TLB structures so that its value matches the maximum value of MAS0[TLBSEL].

00 1 TLB

01 2 TLBs. This is the value presented by the e500.

10 3 TLBs

11 4 TLBs

62–63

MAVN

MMU architecture version number. Indicates the version number of the architecture of the MMU

implemented by the processor. 0b00 indicates version 1.0.

39 40

50 51 52

Field

ASSOC

MINSIZE MAXSIZE IPROT AVAIL

—

NENTRY

Reset

0000_0010

0001

0001_0000_0000

R/W

Read only

SPR

SPR 688

Figure 6-40. TLB Configuration Register 0 (TLB0CFG)

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