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MPC8540 bảng dữ liệu(PDF) 264 Page - Freescale Semiconductor, Inc |
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MPC8540 bảng dữ liệu(HTML) 264 Page - Freescale Semiconductor, Inc |
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264 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 6-14 Freescale Semiconductor Core Register Summary 6.5.2 Processor ID Register (PIR) 6.5.3 Processor Version Register (PVR) 6.5.4 System Version Register (SVR) 32 63 Field Processor ID Reset All zeros R/W Read only SPR SPR 286 Figure 6-7. Processor ID Register (PIR) 32 47 48 63 Field Version Revision Reset 0x8020_nnnn R/W Read only SPR SPR 287 Figure 6-8. Processor Version Register (PVR) Table 6-7. PVR Field Descriptions Bits Name Description 32–47 Version A 16-bit number that identifies the version of the processor. Different version numbers indicate major differences between processors, such as which optional facilities and instructions are supported. 48–63 Revision A 16-bit number that distinguishes between implementations of the version. Different revision numbers indicate minor differences between processors having the same version number, such as clock rate and engineering change level. 32 63 Field System version Reset SoC-dependent value: 0x8030_nnnn R/W Read only SPR SPR 1023 Figure 6-9. System Version Register (SVR) |
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