MPC8540 datasheet(263/1302 Pages) FREESCALE

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Processor Control Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-13

External enable

0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled.

1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled.

User mode (problem state)

0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for

example, GPRs, SPRs, and the MSR).

1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any

privileged resource.

PR also affects memory access control

—

Reserved, should be cleared. 1

Machine check enable

0 Machine check interrupts are disabled.

1 Machine check interrupts are enabled.

—

Reserved, should be cleared. 1

UBLE In the e500, it is the user BTB lock enable bit.

0 Execution of the BTB lock instructions for user mode is disabled; privileged instruction exception

taken instead.

1 Execution of the BTB lock instructions for user mode is enabled.

Debug interrupt enable

0 Debug interrupts are disabled.

1 Debug interrupts are enabled if DBCR0[IDM] = 1.

See the description of the DBSR[UDE] in Section 6.13.2, “Debug Status Register (DBSR).”

55–57

—

Reserved, should be cleared. 1

Instruction address space

0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB entry).

1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB entry).

Data address space

0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB entry).

1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB entry).

—

Reserved, should be cleared. 1

PMM Performance monitor mark bit (defined by the EIS). System software can set PMM when a marked

process is running to enable statistics to be gathered only during execution of the marked process.

MSR[PR] and MSR[PMM] together define a state that the processor (supervisor or user) and the

process (marked or unmarked) may be in at any time. If this state matches an individual state specified

in the PMLCax, the state for which monitoring is enabled, counting is enabled.

62–63

—

Preserved for OEA-defined RI and LE, respectively

1 An MSR bit that is reserved may be altered by a return from interrupt instruction.

Table 6-6. MSR Field Descriptions (continued)

Bits

Name

Description

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