LM3655 datasheet(8/21 Pages) NSC

8 / 21 page

11.0 Charge Control Functions (Continued)

Specification

Test Conditions

Min

Typ

Max

Units

Debounce Connection Delay “

DEBOUNCE_ON”IDETECT stepped from 0 mA to 1 mA

Debounce Connection Delay “

DEBOUNCE_OFF”IDETECT stepped from 1 mA to 0 mA

11.2.3 Power Supply Test Pulses

The purpose of the test pulse operation is for the IC to periodically test the charging power supply’s full-rate current capability. This

operation only occurs when the cell voltage is above V

PHONE_ON. The test pulse has a period of

TEST_PERIOD and pulse width

TEST_WIDTH. During test pulses the IC will fully turn on the M5 pass devices and attempts to draw ICHRG_MAX current from the

charging power supply. The charging power supply will respond by delivering the full-rate current up to I

CHRG-MAX to the load (Q1

will be forced into saturation). During the test pulse, the IC constantly monitors the cell voltage with its internal voltage regulation

control circuit and the charge current with its current regulation control circuit. The power dissipation of Q1 is not controlled during

the test pulse. The IC determines which charge rate to apply at the end of each test pulse.

The interaction between the three control circuits is such that the voltage regulation is the most dominant so the cell voltage will

not exceed V

TERMX.(VTERMX being either VTERMH or VTERML, depending on the logic level applied to the CHEMISTRY pin). When

the test pulse is high, one of the following can occur:

1. V

PHONE_ON < VCELL < VTERMX and Charge Current < ICHRG_MAX:

The charging power supply will continue to deliver full-rate current during and after the test pulse. Q1 remains in saturation and

all M5 sense resistor switches remain on.

2. V

PHONE_ON < VCELL < VTERMX and Charge Power Supply wants to deliver more than ICHRG_MAX (e.g. Failed Vehicular Power

Adaptor and phone is connected directly to car battery):

The internal current regulation control of the LM3655 IC will try to maintain the charge current at I

CHRG_MAX by forcing the external

Q1 and Q2 transistors into linear operation. This may exceed Q1 power dissipation limit. After the test pulse, the IC internal power

regulation control senses the voltage across Q1 V

CE above Q1UNSAT and determines the appropriate M5 sense resistor array

switches to turn on. The effective resistance will determine the amount of charge current allow such that Q1 power dissipation is

within limit of P

PASS_MAX.

If Q1

UNSAT is exceeded at the end of a test pulse, CHRG_STATE will not go high as the Top-off signal is only created when VCELL

reaches V

TERMX. Unless a non-supported power supply is used, because of burp mode, it is expected that the system will mend

itself and go back into full-rate when the next test pulse comes along.

3. V

CELL reaches VTERMX (desired maximum cell clamp level):

The IC internal voltage regulation control will dominate the charger control logic, and control the charge current to maintain V

CELL

at V

TERMX. To accomplish this, the voltage regulation control forces Q1 and Q2 from saturation back in linear mode to reduce the

charge current to a level that will maintain V

CELL at VTERMX. After the test pulse, Q1 VCE above Q1UNSAT indicates the charge

current to be reduced to trickle current. Q1 may or may not be in power-limit regulation.

In order to prevent a transient situation when transitioning from trickle to full-rate between test pulses, the voltage regulation

control will reset to zero for

TEST_DELAY and the current regulation control will then be forced to turn off Q1 and Q2. This in effect

will set the charge current to zero. After

TEST_DELAY the voltage regulator will be allowed to ramp back up and the charge current

will also ramp from zero to full-rate current. Figure 3 illustrates the charge profile.

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