PI7C9X752 datasheet(29/47 Pages) DIODES

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April 2019

Diodes Incorporated

PI7C9X752

Document Number DS40312 Rev 3-2

A product Line of

Diodes Incorporated

PI7C9X752

Receiver Break Error Flag

0 = No Break Error

1 = break condition occurred in data to be read from RX FIFO(RX was LOW for at least one character

frame time).

Receiver Data Framing Error Flag

0 = No Data Framing Error

1 = framing error occurred in data to be read from RX FIFO(The receive character did not have a

valid stop bits).

Receiver Data Parity Error Flag

0 = No Data Parity Error

1 = parity error in data to be read from RX FIFO

Receiver Overrun Error

0 = No Overrun Error

1 = additional data received while the RX FIFO is full. This data should not be transferred into FIFO.

Receiver Data Ready Indicator

0 = No data in received in RX FIFO

1 = Data has been received and saved in the RX FIFO

Offset 06H(default=x0H)--- Modem Status Register (MSR). Accessible when LCR[7]=0 and MCR[6]=0.

Bit

Type

Description

CD input status

Normally this bit is the complement of the CD# input.

In the loopback mode this bit is equivalent to MCR[3]

RI input status

Normally this bit is the complement of the RI# input.

In the loopback mode this bit is equivalent to MCR[2]

DSR input status

Normally this bit is the complement of the DSR# input.

In the loopback mode this bit is equivalent to MCR[0]

CTS input status

Normally this bit is the complement of the CTS# input.

In the loopback mode this bit is equivalent to MCR[1]

Delta CD# input flag

0 = No change on CD# input

1 = The CD# input has changed state. A modem status interrupt will be generated if MSR interrupt is

enabled.

Delta RI# input flag

0 = No change on RI# input

1 = The RI# input has changed from a LOW to HIGH. A modem status interrupt will be generated if

MSR interrupt is enabled

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