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April 2019

Diodes Incorporated

PI7C9X752

Document Number DS40312 Rev 3-2

A product Line of

Diodes Incorporated

PI7C9X752

10.3.2 Auto Address Detection

If Special Character Detect is enabled (EFR[5] is set and XOFF2 contains the address byte) the receiver will try to detect an address

byte that matches the programmed character in XOFF2. If the received byte is a data byte or an address byte that does not match the

programmed character in XOFF2, the receiver will discard these data. Upon receiving an address byte that matches the XOFF2 char-

acter, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along

with the parity bit (in place of the parity error bit). The receiver also generates a line status interrupt (IER bit 2 must be set to 1 at this

time). The receiver will then receive the subsequent data from the ‘master’ station until being disabled by the controller after having

received a message from the ‘master’ station.

If another address byte is received and this address byte does not match XOFF2 character, the receiver will be automatically disabled

and the address byte is ignored. If the address byte matches XOFF2 character, the receiver will put this byte in the RX FIFO along with

the parity bit in the parity error bit (LSR[2]).

11. Host Interface

The host interface is 8 data bits wide with 8 address lines and control signals to execute data bus read and write transactions.

The PI7C9X752 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550

UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# IOR#

and IOW# or CS#, R/W#, All two UART channels share the same data bus for host operations. Please refer to pin description and host

interface read/write timing(Fig 10 and Fig 11).

11.1 UART Channel Selection

During Intel Bus Mode (16/68# pin is connected to VCC), a logic 0 on chip select pins, CSA# or CSB# allows the user to select UART

channel A or B to configure, send transmit data and/or unload receive data to/from the UART. Selecting all two UARTs can be useful

during power up initialization to write to the same internal registers, but do not attempt to read from all two uarts simultaneously.

Individual channel select functions are shown in Table 11.

Table 11. Channel A-B Select In 16 Mode

CSA#

CSB#

Function

1

1

UART de-selected

0

1

Channel A selected

1

0

Channel B selected

0

0

Channel A-B selected

During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for connection with Mo-

torola, and other popular microprocessor bus types. In this mode the V654 decodes two additional addresses, A3 and A4, to select one

of the two UART ports. The A3 and A4 address decode function is used only when in the Motorola Bus Mode. See Table 12.

Table 12. Channel A-B Select In 68 Mode

CS#

A3

Function

1

X

UART de-selected

0

0

Channel A selected

0

1

Channel B selected