TC35680FSG datasheet(20/91 Pages) TOSHIBA

20 / 91 page

TC35680FSG-002/TC35681FSG-002

2019-04-04

Power Supply System

TC35680/TC35681 integrate a DC/DC converter and multiple LDO regulators. Many circuits in the device are supplied with power

from step-down power supply. Power Management Unit (PMU) switches the power supplies dynamically and controls the output

voltage to optimize power efficiency according to low power modes.

The power dedicated to the digital interface can be supplied on the VDDIO pin. So system design or user application need not care

about the power control done by the PMU.

For details of the power supply system, refer also to Section 3.6 and Section 4.4.

Clock System

The frequency of the reference operation clock is 32 MHz. And the frequency of the sleep clock is 32.768 kHz. Each clock circuit has

its own clock divider, so each block including the CPU can be supplied with an optimized clock. For the setting parameters for each

block, refer to the function description in Chapter 4. For the details of the reference clock and the sleep clock, refer to Section 4.12

and Section 4.13, respectively.

The source of the sleep clock of TC35680/TC35681 can be selected from among the following three clock sources. At start-up, the

built-in silicon oscillator (hereafter, SiOSC) is used.



SiOSC



Crystal resonator (A crystal oscillation circuit is used.)



External sleep clock input

The frequency accuracy of the SiOSC is not compliant with the Bluetooth® connection. It cannot be used for the application which

executes the Bluetooth® connection. The SiOSC can be used for application which includes advertising only, and others.

For the details of the sleep clock, refer to Section 4.13.

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