TC35679FSG-002

2018-01-17

15

4.2. Reset Interface (Power up sequence)

4.2.1.

Features

Reset interface has the following features.



1.8 to 3.6 V operation



Level sensitive asynchronous reset (Low level: reset)

When the power supply is applied, the external reset signal connected to the TC35679 should be held the reset state (RESETX =

Low). Please release the reset (RESETX = High) after the power supply voltage reaches 1.8 V or more and becomes stable.

Then, the oscillation of a crystal oscillator is started, and the internal reset is released by the internal timer after the oscillation-stable

time of the crystal oscillator is passed.

4.2.2.

Connection Example

Figure 4-2 shows connection example where TC35679 is powered through RC time constant circuit.

Reset signal can be given from power supply through RC time constant circuit, or can be connected with an IC which has

asynchronous and level sensitive reset function. Figure 4-3 shows the timings to reset and reset-release for the power supply.

Figure 4-2 Reset signal connection example

Figure 4-3 Power-on reset release sequence

VDDIO Power supply

Reset signal

-> Necessary for a reset release after VDDIO stabilization

Reference clock

Oscillation

VBAT Power supply

Sleep clock

(in case of external

oscillator connection)

Operation starts

Sleep clock

(in case of crystal

oscillator connection)

Oscillation

-> It can be input after VDDIO stabilization

So as not to VBAT<VDDIO

It may be input after stabilization of reference clock

Internal LDO

DC/DC converter

LDO On

DC/DC On

System changes an internal power after sleep clock detection

(It enters temporarily to Sleep mode.)

Boot completion

1.8 V or more at startup

Boot starts

TC35679

Reset

Power Supply

Some parts of the connection example are omitted or simplified.