ES25P40 datasheet(7/35 Pages) EXCELSEMI

7 / 35 page

ES I

Rev. 0D May 11 , 2006

ES25P40

Excel Semiconductor inc.

ADVANCED INFORMATION

Protection Modes

The SPI memory device boasts the following data

protection mechanisms

1) All instructions that modify data must be preceded

by a Write Enable(WREN) instruction to set the

Write Enable Latch (WEL) bit. This bit is returned to

its reset state by the following events :

- Power-up

- WRDI instruction completion

- WRSR instruction completion

- PP instruction completion

- SE instruction completion

- BE instruction completion

2) The Block Protect (BP2, BP1, BP0) bits allow part

of the memory to be configured as read-only. This is

the Software Protected Mode (SPM).

3) The Write Protect (W#) signal works in coopera-

tion with the Status Register Write Disable (SRWD)

bit to enable write-protection. This is the Hardware

Protected Mode (HPM).

4) Program, Erase and Write Status Register instruc-

tions are checked to verify that they consist of a

number of clock pulses that is a multiple of eight,

before they are accepted for execution.

If the falling edge does not coincide with Serial Clock

(SCK) being Low, the Hold condition starts after

Serial Clock (SCK) next goes Low. Similarly, If the

rising edge does not coincide with Serial Clock

(SCK) being Low, the Hold condition ends after

Serial Clock (SCK) next goes Low (Figure 3).

During the Hold condition, the Serial Data Output

(SO) is high impedance, and Serial Data Input (SI)

and Serial Clock (SCK) are Don’t Care.

Normally, the device remains selected, with Chip

Select (CS#) driven Low, for the entire duration of

the Hold condition. This ensures that the state of the

internal logic remains unchanged from the moment

of entering the Hold condition.

If Chip Select (CS#) goes High while the device is in

the Hold condition, this has the effect of resetting the

internal logic of the device. To restart communication

with the device, it is necessary to drive Hold

(HOLD#) High, and then to drive Chip Select (CS#)

Low. This prevents the device from going back to the

Hold condition.

Table 1. Protected Area Sizes

Protected Memory

Area (Top Level)

Status Register Content

Memory Content

BP2 Bit

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

none

00000 ~ 7FFFF

1 / 8

70000 ~ 7FFFF

00000 ~ 6FFFF

1 / 4

60000 ~7FFFF

00000 ~ 5FFFF

1 / 2

40000 ~ 7FFFF

00000 ~ 3FFFF

All

00000 ~ 7FFFF

+ parameter page

none

All

00000 ~ 7FFFF

+ parameter page

none

All

00000 ~ 7FFFF

+ parameter page

none

All

00000 ~ 7FFFF

+ parameter page

none

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