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ES25P40 bảng dữ liệu(PDF) 21 Page - Excel Semiconductor Inc. |
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ES25P40 bảng dữ liệu(HTML) 21 Page - Excel Semiconductor Inc. |
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21 / 35 page ![]() ES I ES I 21 Rev. 0D May 11 , 2006 ES25P40 Excel Semiconductor inc. ADVANCED INFORMATION 1 0 1 1 1 0 0 1 Deep Power Down (DP) The Deep Power Down (DP) instruction puts the device in the lowest current mode of 1uA typical. It is recommended that the standard Standby mode be used for the lowest power current draw, as well as the Deep Power Down (DP) as an extra software protection mechanism when this device is not in active use. In this mode, the device ignores all Write, Program and Erase instructions. Chip Select (CS#) must be driven Low for the entire duration of the sequence. The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire dura- tion of the sequence. The instruction sequence is shown in Figure 16. Driving Chip Select (CS#) High after the eighth bit of the instruction code has been latched puts the device in Deep Power Down mode. The Deep Power Down mode can only be entered by executing the Deep Power Down (DP) instruc- tion to reduce the standby current (from ISB to IDP as specified in Table 6). As soon as Chip Select (CS#) is driven high, it requires a delay of tDP cur- rently in progress before Deep Power Down mode is entered. Once the device has entered the Deep Power Down mode, all instructions are ignored except the Release from Deep Power Down (RES) and Read Electronic Signature. This releases the device from the Deep Power Down mode. The Release from Deep Power Down and Read Electronic Signature (RES) instruction also allows the Electronic Signa- ture of the device to be output on Serial Data Out- put (SO). The Deep Power Down mode automatically stops at Power-down, and the device always powers up in the Standby mode. Any Deep Power Down (DP) instruction, while an Erase, Program or WRSR cycle is in progress, is rejected without having any effect on the cycle in progress. Figure 16. Deep Power Down ( DP ) Instruction Sequence CS# SI Standby Mode Instruction Deep Power Down Mode tDP 0 1 2 3 4 5 6 7 SCK |
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