ADF4377 datasheet(62/79 Pages) AD

62 / 79 page

Data Sheet

ADF4377

analog.com

Rev. 0 | 62 of 79

Figure 134.

Table 71. Bit Descriptions for REG0020

Bits

Bit Name

Description

Reset

Access

[7:6]

R020_RSV5

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV4

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

RST_SYS

Reset Digital Functions to POR State. Does not reset the SPI interface and SPI registers. This bit is not

self-clearing.

0x0

R/W

0: reset inactive. Normal operation.

1: reset active.

EN_ADC_CLK

Enable the ADC Clock. See Figure 70.

0x0

R/W

0: disabled.

1: enabled. Normal operation.

R020_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV2

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV1

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x21, Reset: 0x00, Name: REG0021

Figure 135.

Table 72. Bit Descriptions for REG0021

Bits

Bit Name

Description

Reset

Access

[7:4]

R021_RSV7

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

[3:0]

R021_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x22, Reset: 0x00, Name: REG0022

Figure 136.

Table 73. Bit Descriptions for REG0022

Bits

Bit Name

Description

Reset

Access

[7:0]

R022_RSV0[7:0]

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x23, Reset: 0x00, Name: REG0023

ADF4377 bảng dữ liệu(PDF) 62 Page - Analog Devices

ADF4377 bảng dữ liệu(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

bảng dữ liệu tải về

Link URL