FLEX6000 datasheet(38/52 Pages) ALTERA

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Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet

tREG_TO_REG

LUT delay for LE register feedback in carry chain

tCASC_TO_REG

Cascade-in to register delay

tCARRY_TO_REG

Carry-in to register delay

tDATA_TO_REG

LE input to register delay

tCASC_TO_OUT

Cascade-in to LE output delay

tCARRY_TO_OUT

Carry-in to LE output delay

tDATA_TO_OUT

LE input to LE output delay

tREG_TO_OUT

tSU

LE register setup time before clock; LE register recovery time after

asynchronous clear

LE register hold time after clock

tCO

LE register clock-to-output delay

tCLR

LE register clear delay

LE register control signal delay

tLD_CLR

Synchronous load or clear delay in counter mode

tCARRY_TO_CARRY Carry-in to carry-out delay

tREG_TO_CARRY

tDATA_TO_CARRY

LE input to carry-out delay

tCARRY_TO_CASC

Carry-in to cascade-out delay

tCASC_TO_CASC

Cascade-in to cascade-out delay

tREG_TO_CASC

tDATA_TO_CASC

LE input to cascade-out delay

tCH

LE register clock high time

tCL

LE register clock low time

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