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L99MOD51XP bảng dữ liệu(PDF) 15 Page - STMicroelectronics |
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L99MOD51XP bảng dữ liệu(HTML) 15 Page - STMicroelectronics |
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15 / 33 page ![]() DS12667 Rev 6 15/33 L99MOD51XP SPI - electrical characteristics 32 Note: DI timing parameters tested in production by a passed/failed test: Tj = -40 °C/+25 °C: SPI communication @ 2 MHz. Tj = +125 °C: SPI communication @ 1.25 MHz. Note: See Figure 3 and Figure 4. Note: See Figure 5 and Figure 6. Note: See Figure 7. Table 15. DO Symbol Parameter Test condition Min. Typ. Max. Unit VDOL Output low level VCC = 5 V, ID = -4 mA 0.2 0.4 V VDOH Output high level VCC = 5 V, ID = 4 mA VCC -0.4 VCC -0.2 V IDOLK Tristate leakage current VCSN = VCC, 0 V < VDO < VCC -10 10 μA CDO (1) Tristate input capacitance VCSN = VCC, 0 V < VCC < 5.3 V 10 15 pF 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 16. DO timing Symbol Parameter Test condition Min. Typ. Max. Unit tr DO DO rise time CL = 100 pF, Iload = -1 mA 80 140 ns tf DO DO fall time CL = 100 pF, Iload = 1 mA 50 100 ns ten DO tri L DO enable time from tristate to low level CL = 100 pF, Iload = 1 mA pull-up load to VCC 100 250 ns tdis DO L tri DO disable time from low level to tristate CL = 100 pF, Iload = 4 mA pull-up load to VCC 380 450 ns ten DO tri H DO enable time from tristate to high level CL =100 pF, Iload = -1 mA pull-down load to GND 100 250 ns tdis DO H tri DO disable time from high level to tristate CL = 100 pF, Iload = -4 mA pull-down load to GND 380 450 ns td DO DO delay time VDO < 0.3 VCC, VDO > 0.7VCC, CL = 100 pF 50 250 ns Table 17. EN, CSN timing Symbol Parameter Test condition Min. Typ. Max. Unit tEN_CSN_LO Minimum EN high before sending first SPI frame, i.e. CSN going low Transfer of SPI-command to input register 20 50 μs tCSN_HI,min Minimum CSN HI time between two SPI frames Transfer of SPI-command to input register 24 μs |
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