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HVLED001BTR bảng dữ liệu(PDF) 20 Page - STMicroelectronics |
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HVLED001BTR bảng dữ liệu(HTML) 20 Page - STMicroelectronics |
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20 / 33 page ![]() Application information HVLED001B 20/33 DS12748 Rev 2 7.1.2 Ramp-up mode This is a particular operational mode, identical to active mode, where timed protections (Brownout and Over Power Protection - see relevant graphs) are ignored. This mode ends after a fixed period (Tss) since the first crossing upwards of VCC voltage. After Tss, the IC enters active mode. 7.1.3 Active mode This is the normal operational mode. During this state the external MOSFET is driven according to signals coming from the application in order to regulate the desired output parameter in closed loop (peak current control method). Active mode is exited when abnormal conditions are present or VCC drops below the VCC,su threshold. The HVSU is inactive during active mode. 7.1.4 Low consumption mode This state is intended to stop the switching activity reducing the power consumption to a minimum level. During this state the VCC is kept between VCC,su and VCC,on by the high voltage startup unit (HVSU) delivering Icharge to the output capacitor. 7.1.5 Stop mode This state is intended to stop the switching activity without turning off the entire function set, to quickly restart when abnormal or disabling conditions end. During this state the power consumption is not minimized and the HVSU is not enabled. In case the OPTO pin drops below the disabling threshold or VCC voltage drops below the VCC,su voltage and the IC state evolves into low consumption state. Note: IMPORTANT: HVSU charges VCC so any other external voltage (including auxiliary winding) must be de-coupled using a Diode (e.g. 1N4148). 7.2 Control loop The control loop is based on the current mode Quasi Resonant flyback control scheme and is therefore performed turning off the MOSFET when the peak of its source current reaches the threshold set by the control loop, and turning the MOSFET on in correspondence with the resonant valley following the primary side demagnetization input. A detail of the block involved in this scheme is shown in Figure 20. |
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