L9788 datasheet(51/264 Pages) STMICROELECTRONICS

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DS12308 Rev 4

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L9788

Watchdog

263

The counter PWR_CNT is a 3 bit counter.

Behaviour of PWR_CNT:



asynchronous reset to "000" with RST_UV



synchronous reset to "000" IF (EC < 5)



IF (PWR_CNT < 7) AND (sequencer-run AND "EC" > 7) THEN PWR_CNT =

PWR_CNT + 1 ELSE unchanged.

The counter cannot be decremented and can be only reset to "000" by an active RST_UV

signal (asynchronous) or <WDA_INT> = '0' (synchronous).The signal PWR_INT becomes

active '1' when PWR_CNT = "111" and a further error is detected. When KEY_IN =0, the

active PWR_INT signal causes a shut-down of the main relay and the voltage regulators.

This function ensures a secure shutdown of the system in an error state of the µC in "power-

latch". Signal PWR_INT is set to '0' again only when <WDA_INT> = '0'.

4.1.3

Generation of a monitoring module reset

The monitoring module may cause a reset at the pin [RSTN] named "monitoring module

reset" in conjunction with the internal signal WDA_RST. The generation of a monitoring

module reset depends on the state of the bit <WDA_INT>.

< WDA_INT> = '0' (reset state):

If < WDA_INT> = '0', the signal <WDA_RST> remains always inactive '0' and the monitoring

module can never generate a reset. The error counter can only be decremented via correct

responses. If < WDA_INT> = '0' the state of the reset counter <RST_CNT> remains

unchanged when an ERROR COUNTER overflow occurs (description of the reset counter

<RST_CNT> see below).

< WDA_INT> = '1':

If < WDA_INT> = '1', an ERROR COUNTER overflow activates a reset [RST] (signal

<WDA_RST> becomes active). The signal <WDA_RST> becomes active (i.e. '1') due to an

ERROR COUNTER overflow when the value of the 3 bit reset counter <RST_CNT(2-0)> is

0..6. If the value of <RST_CNT> = "111" and an ERROR COUNTER overflow occurs

<WDA_RST> remains inactive (i.e. '0') and no reset is generated. The "reset counter"

<RST_CNT> is incremented by one during a sequencer-run due to an ERROR COUNTER

overflow when < WDA_INT> = '1' and <RST_CNT> is between 0 and 6. If <RST_CNT> = 7

and an ERROR COUNTER overflow occurs, the counter state remains 7. The counter can

not be decremented and can only reset to zero by an active RST_UV signal. The

occurrence of a monitoring module reset is indicated via the flag <WDA_RST> = '1'.

Reading the flag via MSC clears it automatically. In effect maximum 7 monitoring module

resets can be generated between 2 active RST_UV signal. (see also state table for <

WDA_INT> = '1' below).The state of the "reset counter" <RST_CNT> can be read via MSC

but cannot be changed.

Table 20. Internal states for WDA_INIT=1

RST_CNT old value

EC>7 and sequencer-run

RST_CNT new value

WDA_RST

000 … 111

False

= RST_CNT old

0, no monitoring module reset

000 … 110

True

= RST_CNT old + 1

1, monitoring module reset

generated

111

True

= 111

0, no monitoring module reset

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