L9966 datasheet(52/122 Pages) STMICROELECTRONICS

52 / 122 page

Figure 26. Write access (32 bits frame)

16 bit instruction

16 bit data

check byte

zz + 14 bit

previous register

content

GADG1001180956PS

Figure 27. Read access (32 bits frame)

16 bit instruction

xxxxxxxxxxxxxxxx

check byte

zz + 14 bit

16 bit data

GADG1001181056PS

13.2

Address multiplexing

The chip features hardware configurable address multiplexing which allows 2 ICs sharing all the SPI bus, CS line

included.

The first two bits of the SPI frame are used to address the chip. The MSB is always ‘1’ while the second address

bit depends on the level of the CTRL_CFG pin, latched during the transition from WAKE to INIT at power up, see

Table 32. CTRL_CFG hardware address.

In case of open, the CTRL_CFG pin is internally pulled up, see Table 33. CTRL_CFG electrical parameters.

Table 32. CTRL_CFG hardware address

Bit 31

Bit 30

Chip address

0 (CTRL_CFG pin low)

1 (CTRL_CFG pin high)

The chip does not shift out any bit on MISO line unless the correct address is decoded.

Table 33. CTRL_CFG electrical parameters

Symbol

parameter

condition

Min

Typ

Max

Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

VinH

CTRL_CFG input voltage levels

VinL

CTRL_CFG input voltage levels

0.8

Vhys

CTRL_CFG input voltage hysteresis

0.15

0.5

CTRL_CFG_pu

CTRL_CFG pull up to 3V3

100

150

kΩ

L9966

Address multiplexing

DS12459 - Rev 10

page 52/122

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