L9654 datasheet(17/59 Pages) STMICROELECTRONICS

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L9654

Electrical specification

VRES = 6.5 to 35 V, VDD = 4.9 to 5.1V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C

All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.

Table 11. SPI timing

No.

Symbol

Parameter

Min

Typ

Max

Unit

fop

Transfer frequency

5.50

MHz

tSCK

SCLK, SCLK_A Period

181

tLEAD

Enable Lead Time

tLAG

Enable Lag Time

tSCLKHS

SCLK, SCLK_A High Time

tSCLKLS

SCLK, SCLK_A Low Time

tSUS

MOSI, MOSI_A Input Setup Time

tHS

MOSI, MOSI_A Input Hold Time

MISO, MISO_A Access Time

tDIS

MISO, MISO_A Disable Time (1)

1. Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on

the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time,

and minimum capacitance on MISO is the worst case for output hold time.

100

tVS

MISO, MISO_A Output Valid Time

tHO

MISO, MISO_A Output Hold Time (1)

tRO

Rise Time (Design Information)

tFO

Fall Time (Design Information)

tCSN

CS_A, CS_D, CS_S Negated Time

640

Figure 5. SPI timing diagram

Figure 6. SPI timing measurement

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