L9654 datasheet(47/59 Pages) STMICROELECTRONICS

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L9654

Functional description

Figure 20. Manchester decoding using satellite protocol as an example

The decoder uses a counter to track the high to low and low to high transitions at the bit

center. A transition is considered a bit center only when an edge is detected 75% to 125% of

the reference bit time. When a single edge occurs below 75% of the reference bit time it is

considered to be a bit edge but it is ignored. When the decoder detects a second edge

below 75% of the reference bit time the device declares a bit time error via SPI, reverts to

the minimum bit time of the selected range, and waits for idle. When a valid bit center is

detected the counter resets and start counting again until another edge is detected. If the

message is not complete and no edge is detected in the range of 75% to 125% of measured

bit time, the device declares a bit time error via SPI, reverts to the minimum bit time of the

selected range, and waits for idle. The idle time is defined as 150% of the minimum bit time

of the selected protocol speed range. If there is no bit transition detected for that period of

time and the correct number of bits was received, the message is considered complete.

Bit time error and too many bits faults are stored directly into the FIFO once they are

detected without the need to wait till an idle time. Since a bit time error is reported directly

once it is detected before Idle time, too few bits error may never be reported since bit time

error is detected first.

Bit time errors and too many bits errors cause the decoder to revert to the minimum bit time

of the selected range, and discard the message. In case of a message containing multiple

errors only one error code is reported per message, errors detected in the decoding phase

have the following reporting priority; bit time errors, too many bits errors then

communication errors (CRC/Parity).

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