8 / 14 page
U637256
8
March 31, 2006
STK Control #ML0054
Rev 1.0
No.
Software Controlled STORE/RECALL
Cyclek, o
Symbol
Min.
Max.
Unit
Alt.
IEC
27
STORE/RECALL Initiation Time
tAVAV
tcR
70
ns
28
Chip Enable to Output Inactivep
tELQZ
tdis(E)SR
600
ns
29
STORE Cycle Timeq
tELQXS
td(E)S
10
ms
30
RECALL Cycle Timer
tELQXR
td(E)R
20
μs
31
Address Setup to Chip Enables
tAVELN
tsu(A)SR
0ns
32
Chip Enable Pulse Widths, t
tELEHN
tw(E)SR
60
ns
33
Chip Disable to Address Changes
tEHAXN
th(A)SR
0ns
PowerStore and automatic Power Up RECALL
VCC
5.0 V
t
PowerStore
Power Up
VSWITCH
W
DQi
POWER UP
RECALL
BROWN OUT
tRESTORE
tRESTORE
BROWN OUT
PowerStore
(NO SRAM WRITES)
RECALL
(24)
(24)
NO STORE
tPDSTORE
tDELAY
(25)
o:
The software sequence is clocked with E controlled READs.
p:
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
q:
Note that STORE cycles (but not RECALL) are inhibited by VCC < VSWITCH (STORE inhibit).
r:
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s:
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
t:
If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
