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RHRPM4423K02V bảng dữ liệu(PDF) 12 Page - STMicroelectronics |
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RHRPM4423K02V bảng dữ liệu(HTML) 12 Page - STMicroelectronics |
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12 / 31 page ![]() 8 Design guidelines 8.1 Output series resistance The output resistance allows the high frequency operation without exceeding the maximum power dissipation of the driver package. See Section 8.2 Power dissipation to understand how the output resistance value is obtained. For applications with VCC supply voltage greater than 10 V and high capacitive loads (Cg > 10 nF), the dissipated power in the output stage of the device has to be limited, therefore at least 2.2 Ω Rg gate resistor has to be added. Figure 7. Minimum gate resistance is a synthetic view of the boundaries for the safe operation of the RHRPM4423. Figure 7. Minimum gate resistance 10 18 VCC [V] Cg [nF] 10 Rg >2.2Ω GIPD180120161238MT 8.2 Power dissipation The RHRPM4423 embeds two high current low-side drivers which drive high capacitive MOSFETs. This section estimates the power dissipated inside the device in normal applications. Two main terms contribute to the device power dissipation: bias power and driver power. • PDC bias power depends on the static consumption of the device through the supply pins and it is given by below equation: Equation 1 P DC = VCC * ICC • The driver power is the necessary power to continuously switch on and off the external MOSFETs; it is a function both of the switching frequency and total gate charge of the selected MOSFETs. PSW total dissipated power is given by three main factors: – external gate resistance (when present) – intrinsic MOSFET resistance – intrinsic driver resistance RHRPM4423 Design guidelines DS11827 - Rev 3 page 12/31 |
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