VDD = +3.3 V, VSS = GND, C-load = 18 pF (see Figure 5. Phase noise, Fclk = 120 MHz, Vcc = 3.3 V), enabled

(EN = VDD), Tamb = -55 °C to +125 °C, unless otherwise specified.

Symbol

Parameters

Test conditions

Min.

Typ.

Max.

Unit

Output rise time

90%/10%, CL = 18 pF

2.2

ns

90%/10%, CL = 2 pF

0.4

90%/10%, CL = 10 pF(1)

1

1.3

1.6

Output fall time

90%/10%, CL = 18 pF

2.2

90%/10%, CL = 2 pF

0.4

90%/10%, CL = 10 pF(1)

1

1.3

1.6

PhN

Phase noise on Q0

at 250 Hz

Fclk = 16 MHz

-110

dBc

/Hz

at 170 Hz

-100

RMS Jitter

At 1 MHz

4

ps

DL1

Drive level

Crystal using H1 (first harmonic),

100

µW

DL3

Crystal using H3 (third harmonic),

200

Duty-cycle on Q0

45

50

55

%

1. Guaranteed by design and characterization

RHFOSC04

Electrical characteristics

DS13330 - Rev 1

page 6/16