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CC1020-RTR1 bảng dữ liệu(PDF) 24 Page - Texas Instruments

tên linh kiện CC1020-RTR1
Giải thích chi tiết về linh kiện  Single Chip Low Power RF Transceiver for Narrowband Systems
PDF  91 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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CC1020-RTR1 bảng dữ liệu(HTML) 24 Page - Texas Instruments

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CC1020
SWRS046
Page 24 of 92
PCLK
PDI
PSEL
Address
Read mode
6
5
4
3
2
1
0
T
SS
T
CL,min
T
CH,min
T
HS
R
PDO
7
6
5
4
3
2
1
0
Data byte
T
SH
Figure 8. Configuration registers read operation
Parameter
Symbol
Min
Max
Unit
Conditions
PCLK, clock
frequency
FPCLK
10
MHz
PCLK low
pulse
duration
TCL,min
50
ns
The minimum time PCLK must be low.
PCLK high
pulse
duration
TCH,min
50
ns
The minimum time PCLK must be high.
PSEL setup
time
TSS
25
ns
The minimum time PSEL must be low before
positive edge of PCLK.
PSEL hold
time
THS
25
ns
The minimum time PSEL must be held low after
the negative edge of PCLK.
PSEL high
time
TSH
50
ns
The minimum time PSEL must be high.
PDI setup
time
TSD
25
ns
The minimum time data on PDI must be ready
before the positive edge of PCLK.
PDI hold time
THD
25
ns
The minimum time data must be held at PDI, after
the positive edge of PCLK.
Rise time
Trise
100
ns
The maximum rise time for PCLK and PSEL
Fall time
Tfall
100
ns
The maximum fall time for PCLK and PSEL
Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /
90% of VDD. The maximum load that this table is valid for is 20 pF.
Table 14. Serial interface, timing specification



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