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TLD4012 bảng dữ liệu(PDF) 11 Page - Tripath Technology Inc. |
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TLD4012 bảng dữ liệu(HTML) 11 Page - Tripath Technology Inc. |
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11 / 13 page ![]() Tr i p ath Technol ogy, I n c. - Techni cal I n for m ati on 11 TLD4012 – JB/Rev. 2.0a/05.02 APPLICATION INFORMATION Power D i ssipation D e rating for 5x5mm TQFP with Exposed D i e Pad For operating at ambient temperatures above 25 °C the device power dissipation, PDISS, must be de-rated based on a 150 °C maximum junction temperature TJ (max) as given by the following equation: PDISS = (TJ(max) – TA)/θJA Where θJA of the package is determined from the table, and TA is the ambient temperature. θJA,C/W (Copper Pad Soldered To PCB) Airflow (LFPM) 5x5mm 0 34.5 200 29.1 500 27.2 Values apply when the exposed pad is soldered to a JEDEC standard test board. Note that PDISS is the power dissipated on the chip, not PCONS which is the power consumed from the supplies. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink and should be connected to a copper plane on the printed circuit board for optimum heat dissipation. This copper plane must be connected to VSS15. |
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