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TLD4012 bảng dữ liệu(PDF) 1 Page - Tripath Technology Inc. |
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TLD4012 bảng dữ liệu(HTML) 1 Page - Tripath Technology Inc. |
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1 / 13 page ![]() Tr i p ath Technol ogy, I n c. - Techni cal I n for m ati on 1 TLD4012 – JB/Rev. 2.0a/05.02 TLD4012 ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY Technical Information Rev i sion 2.0a – May 2002 GENERAL DESCRIPTION T he T L D4012 is an ADSL line driver that provides very low pow er consumption and low distortion in a very small package as a result of T r ipath’s proprietary pow er processing technology . T h is device accepts differential input signals from an analog front-end (AF E ), and can be used in full-rate ( G.dmt), or G.lite sy stems. T h is T L D4012 offers a low pow er consumption of 650mW for full-rate, full-pow er, CO-side, F D M (non-overlapped) transmissions. APPLICATIONS Full-rate or G.lite line cards DSLAMs DLC equipment Central office switches BENEFITS Reduced line card power Reduced system power Increased line card density More ports per cubic foot of system space Improved system performance Simplifies thermal management on PCB Improved reliability Flexible solution FEATURES Tripath Proprietary Power Processing technology Very low power consumption PCONS(Full-rate ADSL) = 650 mW (typ) PCONS (G.lite) = 390 mW (typ) Low distortion Spurious free dynamic range = -80 dBc 26kHz to 138kHz, RLINE=100Ω, PLINE=19.8dBm Third harmonic distortion = -83 dBc at f = 100 kHz, -82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, VOUT = 10Vpp (differential), 70 Ω load 500 mA minimum output current into a 71 Ω load Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps) Low-power mode -130 mW typical (line terminated -allows reception of incoming signals) Disabled mode - 10 mW typical (no line termination) Over-temperature and over-current protection with Fault output 5x5 mm 32-pin TQFP with exposed die pad Power Processing Block INP Control & Logic Output current limit LOPWR RESETB G0 G1 G2 INN VDD5 GND FAULT REXT OUTN OUTP VSS15 VDD15 VSS5 3 20 21 16 25 15 14 28 6 7 8 4 23 27 13 12 18 11 Block Diagram G3 9 EN_AC 1 FORC_BIAS TH_FAULT AUTO_CLR 31 FBP 30 FBN 29 GND 5 2 GND INP GND EN_AC NC OUTP NC VDD15 NC OUTN NC VSS15 24 17 18 19 20 21 22 23 1 8 7 6 5 4 3 2 (Top View) G2 G0 G1 GND INN 32 31 30 29 28 27 26 25 1 9 10 11 12 13 14 15 16 |
Số phần tương tự - TLD4012 |
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Mô tả tương tự - TLD4012 |
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