HT46C232 datasheet(12/50 Pages) HOLTEK

12 / 50 page

HT46R232/HT46C232

Rev. 1.40

November 23, 2005

CLRWDT times equal one), any execution of the CLR

WDT instruction will clear the WDT. In case

²CLR

WDT1

² and ²CLR WDT2² are chosen (i.e. CLRWDT

times equal two), these two instructions must be exe-

cuted to clear the WDT; otherwise, the WDT may reset

the chip because of time-out.

If the WDT time-out period is selected fs/2

12 (option), the

WDT time-out period ranges from fs/2

12~f

s/2

13, since the

²CLR WDT² or ²CLR WDT1² and ²CLR WDT2²

instructions only clear the last two stages of the WDT.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following...

· The system oscillator turned off but the WDT oscillator

keeps running (if the WDT oscillator or the real time

clock is selected).

· The contents of the on-chip RAM and registers remain

unchanged

· The WDT will be cleared and start recounting (if the

WDT clock source is from the WDT oscillator or the

real time clock)

· All of the I/O ports maintain their original status

· The PDF flag is set and the TO flag is cleared

The system quits the HALT mode by an external reset,

an interrupt, an external falling edge signal on port A or a

WDT overflow. An external reset causes a device initial-

ization and the WDT overflow performs a

²warm reset².

After examining the TO and PDF flags, the reason for

chip reset can be determined. The PDF flag is cleared

by system power-up or by executing the

²CLR WDT² in-

struction and is set when executing the

²HALT² instruc-

tion. On the other hand, the TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the program counter and SP; and leaves the others in

their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by the option. Awakening from an I/O port stimu-

lus, the program will resume execution of the next in-

struction. If it is awakening from an interrupt, two

sequences may occur. If the related interrupt is disabled

or the interrupt is enabled but the stack is full, the pro-

gram will resume execution at the next instruction. But if

the interrupt is enabled and the stack is not full, the regu-

lar interrupt response takes place. When an interrupt re-

quest flag is set to

²1² before entering the HALT mode,

the wake-up function of the related interrupt will be dis-

abled. If wake-up event occurs, it takes 1024 fSYS (sys-

tem clock period) to resume normal operation. In other

words, a dummy period is inserted after wake-up. If the

wake-up results from an interrupt acknowledgment, the

actual interrupt subroutine execution is delayed by more

than one cycle. However, if the wake-up results in the

next instruction execution, this will be executed per-

formed immediately after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset may occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a

²warm reset² that

resets only the program counter and SP, leaves the

other circuits at their original state. Some registers re-

main unaffected during any other reset conditions. Most

registers are reset to the

²initial condition² when the re-

set conditions are met. Examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

f s / 2

S y s t e m C l o c k / 4

D i v i d e r

W D T P r e s c a l e r

M a s k O p t i o n

M a s k

o p t i o n

s e l e c t

W D T

O S C

f s

C K

W D T C l e a r

T i m e - o u t R e s e t

2 / f S ~ 2 / f S

1 5

1 6

1 4

1 5

1 3

1 4

1 2

1 3

Watchdog Timer

R E S

V D D

1 0 0 k W

1 0 k W

0 . 1 m F *

0 . 0 1 m F *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

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