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STM32F405IEH6TR bảng dữ liệu(PDF) 28 Page - STMicroelectronics |
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STM32F405IEH6TR bảng dữ liệu(HTML) 28 Page - STMicroelectronics |
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28 / 201 page  Description STM32F405xx, STM32F407xx 28/201 DocID022152 Rev 6 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (ON or OFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary- coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP64 LQFP100 Yes No Yes No LQFP144 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP90 UFBGA176 LQFP176 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD |
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