DS0147 datasheet(67/128 Pages) MICROCHIP

67 / 128 page

Condition

Unit

Max

Typ

Min

Symbol

Parameter

MHz

FPHDET/56

FPHDET/77

FPHDET/91

FBW

Loop bandwidth

(FRAC)

Max (±60 ps, ±0

.5 degrees)

TSPO

Static phase off-

set of the PLL

outputs

1.5 MHz ≤ Fout

< 15 MHz

0.025*output_

period

TOUTJITTER

PLL output peri-

od jitter

Fout ≥ 15 MHz

135

TOUTDUTY

PLL output duty

cycle precision

μs

Max (6.0 μs, 62

5 PFD cycles)

TLOCK

PLL lock time

PFD cycles

TUNLOCK

PLL unlock time

MHz

1250

0.050

FOUT

PLL output fre-

quency

μs

TMPDPW

Minimum pow-

er-down pulse

width

PFD cycles

1.5

FMAXDFB

Maximum delay

in the feedback

path

3.1

0.1

Mod_Spread

Spread spec-

trum modula-

tion spread

KHz

FPHDETF/(128)

FPHDETF/ (128x6

Mod_Freq

Spread spec-

trum modula-

tion frequency

1. Minimum time for high or low pulse width.

2. Maximum jitter the PLL can tolerate without losing lock.

3. Default bandwidth setting of BW_PROP_CTRL = "01" for Integer and Fraction modes leads to the typical

estimated bandwidth. This bandwidth can be lowered by setting BW_PROP_CTRL = "00" and can be

increased if BW_PROP_CTRL = "10" and will be at the highest value if BW_PROP_CTRL = "11".

4. Maximum (±3-Sigma) phase error between any two outputs with nominally aligned phases.

5. Input clock cycle is REFDIV/FREF. For example, FREF = 25 MHz, REFDIV = 1, lock time = 10.0 (assumes

LOCKCOUNTSEL setting = 4'd8 (256 cycles)).

6. Unlock occurs if two cycles slip within LOCKCOUNT/4 PFD cycles.

7. Maximum propagation delay of external feedback path in Deskew mode.

8. Programmable capability for depth of down spread or center spread modulation.

9. Programmable modulation rate based on the modulation divider setting (1 to 63).

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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