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STM32F405 bảng dữ liệu(PDF) 119 Page - STMicroelectronics

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STM32F405 bảng dữ liệu(HTML) 119 Page - STMicroelectronics

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DS8626 Rev 9
119/203
STM32F405xx, STM32F407xx
Electrical characteristics
5.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 48).
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.
Figure 38. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 51. Otherwise the reset is not taken into account by the device.
Table 51. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)(1)
1. Guaranteed by design.
NRST Input low level voltage
TTL ports
2.7 V
≤ VDD
≤ 3.6 V
--
0.8
V
VIH(NRST)(1) NRST Input high level voltage
2
-
-
VIL(NRST)(1) NRST Input low level voltage
CMOS ports
1.8 V
≤ VDD
≤ 3.6 V
--
0.3VDD
VIH(NRST)(1) NRST Input high level voltage
0.7VDD
--
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
--
200
-
mV
RPU
Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum
(~10% order)
.
VIN = VSS
30
40
50
k
Ω
VF(NRST)(1) NRST Input filtered pulse
-
-
100
ns
VNF(NRST)(1) NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal
Reset source
20
-
-
µs
ai14132c
STM32F
RPU
NRST(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit (1)



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