The PFC is enabled when the AC line crosses the brown-in threshold. The PFC is disabled after 45 ms the AC

line is below the brown-out threshold.

In order to improve AC line reading and avoid false brown-in, the HV DMOS is turned on sinking IXCD current

for 100 ms in case of brown-out or line disconnection events. This function can be enabled / disabled through the

dedicated NVM bit.

10.2.2

Line synchronization

A dedicated digital peripheral manages the PFC synchronization with the AC line sine wave.

In order to improve AC line reading and synchronization, the HV DMOS is turned on sinking IVAC_HV_SINK

current at startup. This function can be enabled / disabled through the dedicated NVM bit.

10.2.3

Line disconnection and X-cap discharge

The Vline_sense is monitored to detect the AC line disconnection in order to discharge the X-cap through the

internal HV DMOS.

The detection is based on AC activity absence on the VAC pin (the X-cap discharge function is triggered if there

is no line activity for more than 50 ms). To discharge the X-cap, the HV DMOS turns on sinking a current of 4 mA

minimum.

In order to improve AC line reading and avoid false brown-in, the HV DMOS is turned on sinking IXCD current

for 100 ms in case of brown-out or line disconnection events. This function can be enabled / disabled through the

dedicated NVM bit.

The discharge current stays on until the VAC pin is discharged or the AC line activity is detected again.

10.2.4

Vline surge stop

A surge can be detected on the VAC pin (430 V).

During the surge the PFC activity is stopped for one half-cycle.

If a line surge is detected during the PFC soft-start, the system shuts down with a not latched fault.

10.2.5

Line monitor for PFC control

A 20 MΩ voltage divider for the AC line monitor is internally connected from the VAC pin to GND.

10.2.6

Early warning signal

If a brown-out or another stopping event (early warning managed faults) is detected, the STNRG011A:

•

Stops the PFC

•

LLC continues switching for about 5 ms, trying to keep the LLC output voltage regulated

•

PFC_FB pin is pulled up to VCore voltage for about 5 ms (early warning signal)

The early warning managed faults are:

•

Brown-out

•

X-cap

•

PFC UVP

•

LLC OLP (only in case of OLP time based management)

If any other faults / events occur, the STNRG011A stops both PFC and LLC and generates an early warning

signal for about 250 µs.

The early warning signal generation is active as soon as the device starts driving the PFC MOSFET.

This function can be enabled / disabled through the dedicated NVM bit.

10.3

Gate-drivers

The HVG and LVG are matched drivers. Deadtimes are programmable by the user.

During the burst-mode sleep phase, the HS BOOT capacitor discharges. The burst packets always start with a

LVG pulse to recharge the bootstrap capacitor. A fast external bootstrap diode is necessary.

STNRG011A

Gate-drivers

DS13973 - Rev 2

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