F1350 datasheet(7/27 Pages) RENESAS

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DPD Demodulator for PA

Linearization, 1300MHz to 2900MHz

IDTF1350

Datasheet

IDT Zero-DistortionTM, Glitch-FreeTM DPD Receiver

January 21, 2020

TO PROGRAM THE SERIAL INTERFACE:

If CSb is de-asserted (set to high), the serial interface will ignore the CLK line. Once CSb is asserted (set to low), the

serial interface will recognize the CLK and any data present on DATA will be clocked into the registers with each

rising CLK edge. After the 16th CLK cycle, and before the 17th CLK cycle, CSb must be de-asserted to successfully

program the part with the desired bytes. If CSb is de-asserted before the 16th CLK cycle, or after the 17th CLK cycle,

there is no guarantee that the correct bytes will be programmed and the user will have to re-program the interface in

accordance with the aforementioned procedure.

SW_LATCH PROGRAMMING SEQUENCE

•

When SW_LATCH is pinned high during the programming sequence, “RFSW” and “ENb” registers cannot be

programmed and therefore will not toggle.

•

If SW_LATCH is pinned low during the programming sequence, the “RFSW” and “ENb” register will

toggle. This can be prevented with the “Programming Sequence” below.

SEQUENCE FOR PROGRAMMING REGISTERS A<2>:A<0>

1) SW_Latch = 1; CSb = 0

2) CLK in 8- or 16-bit word, do not de-assert (pull high) CSb

3) Set SW_LATCH = 0 while CSb = 0 remains)

4) With SW_Latch = 0, set CSb = 1

5) Set SW_Latch = 1

6) Program complete

SPECIAL NOTE REGARDING PHASE OF I & Q:

• When LO is high-side injected, IF_Q leads IF_I by 90 degrees

• When LO is low-side injected, IF_I leads IF_Q by 90 degrees

SDATA

SCLK

RFSW

ENb

CSb (solid)

SW_LATCH (dashed)

RFSW

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