TAS2780 datasheet(21/97 Pages) TI

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8.4.2.2 Amplifier Inversion

The TAS2780 will output a non-inverted signal to the OUT_P and OUT_N pins. The output can be inverted with

respect to the digital input value by setting the AMP_INV register bit to high.

8.4.2.3 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier output level and the digital

volume control (DVC).

Amplifier output level settings are programmed using the AMP_LEVEL[4:0] register bits. The amplifier levels are

presented in Section 8.9.8.The Digital Volume Control (DVC) is set by default to 0 dB. It should be noted that

these levels may not be achievable because of analog clipping in the amplifier, so they should be used only to

convey gain.

Equation (1) calculates amplifier output voltage:

VAMP= INPUT+ADVC+AAMP

(1)

where

• VAMP is the amplifier output voltage in dBV

• INPUT is the digital input amplitude as a number of dB with respect to 0 dBFS

• ADVC is the digital volume control setting as a number of dB

• AAMP is the amplifier output level setting as a number of dBV

The DVC is configurable from 0 dB to -100 dB in 0.5 dB steps by setting the DVC_LVL[7:0] register bits. Settings

greater than C8h are interpreted as mute. When a change in digital volume control occurs, the device ramps the

volume to the new setting based on the DVC_RAMP_RATE[1:0] register bits status.

If DVC_RAMP_RATE[1:0] bits are set to 2'b11 the volume ramping is disabled. This setting can be used

to speed up startup, shutdown and digital volume changes when volume ramping is handled by the system

controller.

The Class-D amplifier uses a closed-loop architecture. The approximate threshold for output signal clipping is

given by equation (2).

(2)

where:

• VPK is the maximum peak un-clipped output voltage in V

• VSUP is the power supply of Class-D output stage

• RL is the speaker load in Ω

• RP is the parasitic resistance on PCB (routing, filters) in Ω

• RFET is the power stage total resistance (HS FET, LS FET, Sense Resistor, bonding, packaging) in Ω

When VBAT1S supplies Class-D output stage typical RFET value is 0.5 Ω. For PVDD supply RFET typical value is

0.25 Ω.

8.4.2.3.1 Safe Mode

The safe mode is a single bit that will enable an 18 dB attenuation in the forward path. It is similar to setting the

DVC_LVL[7:0] register bits to 24h (-18 dB). When the SMODE_EN bit is set to high, the DVC_LVL[7:0] register

bits will be ignored and volume ramping disabled.

8.4.2.4 VBAT1S Supply

The TAS2780 can operate with or without an external VBAT1S supply. When configured without an external

VBAT1S supply, the PVDD voltage will be used with an internal LDO to generate this supply voltage. A

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TAS2780

SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022

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