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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS2780 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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TAS2780 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 97 page  TA = 25 °C, PVDD = 18 V, VBAT1S = 3.8 V, AVDD = 1.8V, IOVDD =1.8 V, RL = 4Ω + 15µH, fin = 1 kHz, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, NG_EN=0, EN_LLSR=0, PWR_MODE1(2), measured filter free as in Section 7 (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIAGNOSTIC GENERATOR THD+N Total Harmonic Distortion and Noise Pout = 1 W -82 dB ferr Frequency Error Using internal oscillator: DG_CLK = 0 2 % DIE TEMPERATURE SENSOR Resolution 8 bits Minimum Temperature Measurement Range -40 °C Maximum Temperature Measurement Range 150 °C Die Temperature Resolution 1 °C Die Temperature Accuracy -5 5 °C VOLTAGE MONITOR Resolution 12 bits PVDD Measurement Range Minimum Level 2 V Maximum Level 23 PVDD Resolution 22.5 mV PVDD Accuracy 2 V ≤ PVDDV ≤ 23 V ±60 mV VBAT1S Measurement Range Minimum Level 2 V Maximum Level 6 VBAT1S Resolution 20 mV VBAT1S Accuracy 2.3 V ≤ VBAT1S ≤ 6 V ±20 mV TDM SERIAL AUDIO PORT Minimum PCM Sample Rates and FSYNC Input Frequency 44.1 kHz Maximum PCM Sample Rates and FSYNC Input Frequency 96 Minimum SBCLK Input Frequency I2S/TDM Operation 0.7056 MHz Maximum SBCLK Input Frequency I2S/TDM Operation 24.576 SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 0.5 ns RMS Jitter above 40 kHz that can be tolerated without performance degradation 1 Minimum SBCLK Cycles per FSYNC in I2S and TDM Modes Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500 16 Cycles Maximum SBCLK Cycles per FSYNC in I2S and TDM Modes Other Values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500 512 PCM PLAYBACK CHARACTERISTICS fs ≤ 48 kHz fs Minimum Sample Rate 44.1 kHz Maximum Sample Rate 48 Frequency for Passband Ripple 0.454 fs Passband Ripple 20 Hz to LPF cutoff frequency -0.15 0.15 dB Stop Band Attenuation ≥ 0.55 fs 60 dB ≥ 1 fs 65 Group Delay (Including Noise Gate) DC to 0.454 fs, DC blocker disabled 19 1/fs www.ti.com TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TAS2780 |
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