25CSM04T-ISLASHMF datasheet(37/55 Pages) MICROCHIP

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DS20005817D-page 37

25CSM04

10.1.4

ADDRESS LOCATION OF THE

MEMORY PARTITION REGISTERS

When attempting to access any of the device’s eight

MPRs, the address of each MPR is embedded in bit

position A18:A16 of the 24-bit address sent to the

device.

The remaining 21 address bits (A23-A19 and A15-A0)

are ignored. Table 10-3 depicts the values needed to

be sent in the A18 through A16 positions.

10.2

Writing to the Memory Partition

Registers

10.2.1

MEMORY PARTITION REGISTER

WRITE ENABLE (PRWE)

Prior to any write sequence to protect an address

boundary, or FRZR instruction, the WEL and PREL bits

in the STATUS register must be set to ‘1’. This is

accomplished by first sending a WREN (06h) instruction,

(see Section 6.1.3 “Write Enable Latch”) followed by

a PRWE (07h) instruction, as shown in Figure 10-3.

Once both bits are set to ‘1’, the MPRs can be

programmed with the WMPR instruction, the Partition

Endpoint Addresses can be set with the PPAB

instruction, or the contents of all MPRs can be

permanently locked with the FRZR instruction. Upon

completion of any of these instructions, the PREL and

WEL bits are automatically reset to logic ‘0’.

FIGURE 10-3:

PARTITION REGISTER WRITE ENABLE (PRWE) INSTRUCTION

TABLE 10-3:

MEMORY PARTITION

LOCATION

Memory Partition

A18

A17

A16

MPR0

MPR1

MPR2

MPR3

MPR4

MPR5

MPR6

MPR7

SCK

234

567

High-Impedance

PRWE Opcode (07h)

000

MSb

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