25CSM04T-ISLASHMF datasheet(25/55 Pages) MICROCHIP

25 / 55 page

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DS20005817D-page 25

25CSM04

6.3

Write STATUS Register (WRSR)

The Write STATUS Register (WRSR) instruction enables

the SPI host to change selected bits of the STATUS

WREN instruction must be executed to set the WEL bit

to logic ‘1’. Upon completion of a WREN instruction, a

WRSR sequence can be executed.

The WRSR instruction will only modify:

• Byte 0: bit 7, bit 3 and bit 2

• Byte 1: bit 7

These modifiable bits are the Write-Protect Enable

(WPEN) bit, the Block Protect (BP1, BP0) bits and the

Write Protection Mode (WPM) bit.

These four bits are nonvolatile cells that have the same

properties and functions as regular EEPROM cells.

Their values are retained while power is removed from

the device. While FMPC (byte 1, bit 5) and PABP

(byte 1, bit 3) of the STATUS register are also

nonvolatile bits, they are modified through dedicated

instructions. Refer to Section 6.1.7 “Freeze Memory

Protection Configuration Bit” and Section 10.1.3

“Protecting the Partition Endpoint Addresses” for

more details about these requirements.

When writing to the STATUS register, byte 0 must

always be written. Byte 1 can optionally be written to

utilize Enhanced Write Protection mode.

The 25CSM04 will not respond to instructions other

than a RDSR or a WRBP after a WRSR sequence until

the self-timed internal write cycle has completed. When

the write cycle has completed, the WEL bit in the

STATUS register is reset to a logic ‘0’.

FIGURE 6-3:

WRITE STATUS REGISTER (WRSR) SEQUENCE

Note:

If the CS pin is deasserted at somewhere

other than the end of an 8-bit byte

boundary, the sequence will be aborted

and no write cycle will take place.

9 1011

1415

SCK

12 13

16 17 18 19 20 21 22 23

High-Impedance

0 0 0 0 000 1 D7 XX X D3 D2 XX D7 XX X X XX X

WRSR Opcode

STATUS Register Byte

MSb

TWC(1)

Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

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