L6711 datasheet(14/38 Pages) STMICROELECTRONICS

14 / 38 page

L6711

14/38

Figure 6. Current Reading Connections selectable through CS_SEL pin.

5.1

LOW SIDE Current Reading

Leaving CS_SEL pin OPEN, the current flowing trough each phase is read using the voltage drop across

the low side mosfets RdsON or across a sense resistor in its series and it is internally converted into a cur-

rent. The transconductance ratio is issued by the external resistor Rg placed outside the chip between

CSx- and CSx+ pins toward the reading points (see Figure 7 right). The proprietary current sense circuit

tracks the current information for a time TTRACK = TSW/3 (TSW = 1/FSW) centered in the middle of the low-

side mosfet conduction time (OFF Time, see Figure 7 left) and holds the tracked information during the

rest of the period.

This device sources a constant 50

µA current from the CSx+ pin: the current reading circuitry uses this pin

as a reference and the reaction keeps the CSx- pin to this voltage during the reading time (an internal

clamp keeps CSx+ and CSx- at the same voltage sinking from the CSx- pin the necessary current during

the hold time; this is needed when LS mosfet RdsON sense is implemented to avoid absolute maximum

rating overcome on CSx- pin). The current that flows from the CSx- pin is then given by the following equa-

tion (See Figure 7 - right):

where

RdsON is the on resistance of the low side mosfet and Rg is the transconductance resistor used between

CSx- and CSx+ pins toward the reading points; IPHASEx is the current carried by the relative phase and

IINFOx is the current information signal reproduced internally.

µA offset allows negative current reading, enabling the device to check for dangerous returning current

between the phases assuring the complete current equalization. From the current information of each

phase, information about the total current delivered (IDROOP = IINFO1 + IINFO2 + IINFO3) and the average

current for each phase (IAVG = (IINFO1 + IINFO2 + IINFO3)/3 ) is taken. IINFOX is then compared to IAVG to give

the correction to the PWMx output in order to equalize the current carried by the three phases.

Figure 7. Current reading across LS mosfet: timing (left) and circuit (right) for each phase.

CSx-

CSx+

LGATEx

IPHASE

CS_SEL

Rg(RC)

CSx+

CSx-

PHASEx

OUT

IPHASE

CS_SEL

Rg(a)

LS Mosfet Current Sense

Inductor Current Sense

CSx-

µA

ds ON

------------------ I

PHASEx

⋅

µAI

INFO x

INFOx

dsON

------------------ I

PHASEx

⋅

IPHASEx

ILSx

IINFOx

TTRACK

TSW

CSx+

CSx-

LGATEx

IPHASEx

µA

ICSx-

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