TMS320VC5441APGF datasheet(66/86 Pages) TI

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Electrical Specifications

December 1999 – Revised April 2002

SPRS122E

5.6

Clock Options

The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in Section 3.2.6.

5.6.1 Divide-By-Two, Divide-By-Four, and Bypass Clock Options – PLL Disabled

The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle. The selection of the clock mode is described in Section 3.2.6.

Table 5–2 and Table 5–3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5–2).

Table 5–2. Divide-By-Two, Divide-By-Four, and Bypass Clock Options Timing Requirements

MIN

MAX

UNIT

tc(CI)

Cycle time, CLKIN

†

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

tw(CIL)

Pulse duration, CLKIN low

tw(CIH) Pulse duration, CLKIN high

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

Table 5–3. Divide-By-Two, Divide-By-Four, and Bypass Clock Options Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

7.5

2tc(CI)

†

tc(CO)

Cycle time, CLKOUT – bypass mode

7.5

2tc(CI)

†

td(CIH-CO)

Delay time, CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high

H–2

H–1

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

tr(CO)

tf(CO)

CLKOUT

CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tc(CO)

tc(CI)

tw(COH)

tw(CIH)

tw(CIL)

Figure 5–2. External Divide-by-Two Clock Timing

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