TMS320VC5441APGF datasheet(53/86 Pages) TI

53 / 86 page

Functional Overview

December 1999 – Revised April 2002

SPRS122E

3.2.8 Chip Subsystem ID Register

The chip subsystem ID register (CSIDR) is a read-only memory-mapped register located at 3Eh within each

DSP subsystem. This register contains two elements for electrically readable device identification. The

Chip ID bits identify the type of C54x

 device (41h for 5441). The SubSysID contains a unique subsystem

identifier. Figure 3–28 shows the CSIDR and Table 3–20 describes its bit functions.

987

43210

Chip ID

Reserved

SubSysID

LEGEND: R = Read

Figure 3–28. Chip Subsystem ID Register (CSIDR)

Table 3–20. Chip Subsystem ID Register Bit Functions

BIT

NO.

BIT FIELD

NAME

FUNCTION

15 8

Chip ID

54x device type Contains 41h for 5441

15–8

Chip ID

54x device type. Contains 41h for 5441.

7–4

Reserved

3 0

SubSysID

Identifier for DSP subsystem: A = 00b B = 01b C = 10b andD=11b

3–0

SubSysID

Identifier for DSP subsystem: A = 00b, B = 01b, C = 10b, and D = 11b

3.2.9 Data Memory Map Register

To access the extended data memory, the DSP CPU need to configure the data memory map register

(DMMR), which is used to point to extended data memory. The content of DMMR register is used to select

the extended data for all CPU data memory accesses. Figure 3–29 shows the DMMR and Table 3–21

describes its bit functions.

987

4321

Reserved

Extended

Data

R/W+0

LEGEND: R = Read, W = Write

Figure 3–29. Data Memory Map Register (DMMR)

Table 3–21. Data Memory Map Register Functions

BIT

NO.

BIT FIELD

NAME

FUNCTION

15–1

Reserved

Extended data

Extended data memory for CPU access:

Extended Data = 0b DARAM2 and DARAM3 are mapped in

Extended data

Extended_Data = 0b, DARAM2 and DARAM3 are mapped in.

Extended_Data = 1b, DARAM4 and DARAM5 are mapped in.

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