AD8384ASVZ datasheet(6/24 Pages) AD

6 / 24 page

AD8384

Rev. 0 | Page 6 of 24

SERIAL INTERFACE

Table 4. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, SVRL = 4 V, SVRH = 9 V, unless otherwise noted

Parameter

Conditions

Min

Typ

Max

Unit

SERIAL DAC REFERENCE INPUTS

SVFS = (SVRH – SVRL)

SVRH Range

SVRL < SVRH

SVRL + 1

AVCC – 3.5

SVRL Range

SVRL < SVRH

AGND + 1.5

SVRH – 1

SVFS Range

SVRH Input Current

SVFS = 5 V

–70

SVRL Input Current

SVFS = 5 V

–2.8

–2.5

SVRH Input Resistance

kΩ

SERIAL DAC ACCURACY

DNL

SVFS = 5 V, RL = ∞

–1.0

+1.0

LSB

INL

SVFS=5 V, RL = ∞

–1.5

+1.5

LSB

Output Offset Error

–2.0

+2.0

LSB

Scale Factor Error

–4.0

+4.0

LSB

SERIAL DAC LOGIC INPUTS

CIN

IIL

–0.6

µA

IIH

0.05

µA

VTH

1.65

VIH

2.0

DVCC

VIL

DGND

0.8

SERIAL DAC OUTPUTS

Maximum Output Voltage

SVRH – 1 LSB

Minimum Output Voltage

SVRL

VAO1—Grounded Mode

0.1

IOUT

±30

CLOAD Low Range6

0.002

µF

CLOAD High Range1

0.047

µF

SERIAL DAC DYNAMIC PERFORMANCE

SEN to SCL Setup Time, t20

SCL, High Level Pulse Width, t21

SCL, Low Level Pulse Width, t22

SDI Setup Time, t24

SDI Hold Time, t25

SCL to SEN Hold Time, t23

VAO1, VAO2 Settling Time, t26

SVFS = 5 V, to 0.5%, CL = 100 pF

µs

VAO1, VAO2 Settling Time, t26

SVFS = 5 V, to 0.5%, CL = 33 µF

6 Outputs VAO1 and VAO2 are designed to drive very high capacitive loads. The load capacitance must be

≤ 0.002 µF or ≥0.047 µF.

Load capacitance in the range 0.002 µF to 0.047 µF causes the output overshoot to exceed 100 mV.

AD8384ASVZ bảng dữ liệu(PDF) 6 Page - Analog Devices

AD8384ASVZ bảng dữ liệu(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL