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16F506 bảng dữ liệu(PDF) 51 Page - Microchip Technology |
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16F506 bảng dữ liệu(HTML) 51 Page - Microchip Technology |
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51 / 114 page ![]() © 2006 Microchip Technology Inc. Preliminary DS41268B-page 49 PIC12F510/16F506 8.0 COMPARATOR VOLTAGE REFERENCE MODULE (PIC16F506 ONLY) The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 8-1) controls the Voltage Reference module shown in Figure 8-1. 8.1 Configuring The Voltage Reference The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. Equation 8-1 determines the output voltages: EQUATION 8-1: 8.2 Voltage Reference Accuracy/Error The full range of VSS to VDD cannot be realized due to construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-1) keep CVREF from approaching VSS or VDD. The excep- tion is when the module is disabled by clearing the VREN bit (VRCON<7>). When disabled, the reference voltage is VSS when VR<3:0> is ‘0000’ and the VRR (VRCON<5>) bit is set. This allows the comparator to detect a zero-crossing and not consume the CVREF module current. The voltage reference is VDD derived and, therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage ref- erence can be found in Section 13.2 “DC Character- istics: PIC12F510/16F506 (Extended)”. REGISTER 8-1: VRCON: PIC16F506 ONLY (ADDRESS: 0Ch) VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR3:VR0 x VDD/32) R/W-0 R/W-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 VREN VROE VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 bit 7 VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn bit 6 VROE: CVREF Output Enable bit(1) 1 = VREF output is enabled 0 = VREF output is disabled bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0> CVREF Value Selection bit When VRR = 1: CVREF= (VR<3:0>/24)*VDD When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD Note 1: When this bit is set, the TRIS for the VREF pin is overridden and the analog voltage is placed on the VREF pin. 2: VREF controls for ratio metric reference applies to Comparator 2 on the PIC12F506 only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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