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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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VSC8540RT bảng dữ liệu(PDF) 11 Page - Microchip Technology |
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VSC8540RT bảng dữ liệu(HTML) 11 Page - Microchip Technology |
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11 / 87 page  2022 Microchip Technology Inc. and its subsidiaries DS60001603E-page 11 VSC8540RT PHY Configuration XTAL2 64 O VDD25A Crystal output, leave unconnected when using single ended reference clock Power VDD1 17 P 1.0V digital core power Power VDD1 34 P 1.0V digital core power Power VDD1A 5 P 1.0V analog power requiring additional PCB power supply filtering Power VDD1A 14 P 1.0V analog power requiring additional PCB power supply filtering Power VDD1A 68 P 1.0V analog power requiring additional PCB power supply filtering Power VDD25A 2 P 2.5V analog power requiring additional PCB power supply filtering Power VDD25A 8 P 2.5V analog power requiring additional PCB power supply filtering Power VDD25A 11 P 2.5V analog power requiring additional PCB power supply filtering Power VDDIO 58 P 2.5V or 3.3V general I/O power Power VDDMAC 22 P 1.5V, 1.8V, 2.5V, or 3.3V RGMII/MII/ RMII MAC power Power VDDMAC 28 P 1.5V, 1.8V, 2.5V, or 3.3V RGMII/MII/ RMII MAC power Power VDDMAC 39 P 1.5V, 1.8V, 2.5V, or 3.3V RGMII/MII/ RMII MAC power Power VDDMAC 44 P 1.5V, 1.8V, 2.5V, or 3.3V RGMII/MII/ RMII MAC power Power VDDMDIO 49 P 1.2V, 1.5V, 1.8V, 2.5V, or 3.3V power for SMI pins R/GMII COL 18 I/O, PD VDDMAC MII collision output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See Section 5.3, Hardware Mode Strapping and PHY Addressing for details. R/GMII CRS 19 I/O, PD VDDMAC MII carrier sense output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See Section 5.3, Hardware Mode Strapping and PHY Addressing for details. R/GMII MII_TXCLK 36 I/O, PD VDDMAC MII transmit clock output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See Section 5.3, Hardware Mode Strapping and PHY Addressing for details. TABLE 3-2: PINS BY FUNCTION |
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