SCY99080CDWR2G datasheet(3/27 Pages) ONSEMI

3 / 27 page

DDA002C

http://onsemi.com

Pin Function Description

Pin No.

Pin Name

Function

Pin Description

Brown−out

Detects low input voltage conditions and stops the controller. An internal

current source sets the hysteresis.

CIG

Warm−up time

A capacitor connected to ground sets the pre−heat time for ballast applica-

tions.

DGS

Synchronous output clamp

A resistor connected between this pin and ground adjusts the maximum on−

time available on Lgs and Hgs pins.

Soft−start

Monitors the soft−start capacitor voltage to recognize end of the soft−start

period, discharges the soft−start capacitor during any IC restart.

R_Fmin

Minimum frequency resistor

Connecting a resistor between this pin and ground, sets the minimum oscil-

lator frequency reached for VFB ≥ 5.1 V

R_Fmax

Maximum frequency

resistor

A resistor connected between this pin and ground sets the maximum fre-

quency excursion reached for VFB ≤ 1.2 V

Optocoupler connection

An optocoupler connected (by collector) between this pin and ground (by

emitter) changes the converter operating frequency. The switching frequency

increases when optocoupler pulls the FB pin down to ground.

OTP_latch

OTP latch input

If the voltage on this pin decreases below 1.5 V, the circuit latches off. This

pin sources 170 mA current so an NTC resistor can be connected directly to

this pin.

Dead time

A resistor connected between this pin and ground sets the deadtime

between drivers.

EN1

Enable input 1

When the voltage level on this pin exceeds a reference level for more than

50 ms, all pulses are stopped and the circuit permanently latches off.

EN2

Enable input 2

When the voltage level on this pin exceeds a reference voltage, the circuit

stops pulsing. The IC auto−restarts via full startup sequence (PFC delay,

pre−heat, soft−start) when EN2 is released.

Lgs

Lower gate signal

Duplicates the lower gate signal for synchronization purposes. On time is

limited based on the Rdgs resistor value.

Hgs

Upper gate signal

Duplicates the upper gate signal for synchronization purposes. On time is

limited based on the Rdgs resistor value.

GND

Ground

The controller ground

Lgd

Low−side driver

Drives the low−side half−bridge MOSFET

Vcc

Controller Supply

Energizing the controller. This pin accepts voltage up to 20 Vdc

Half−Bridge

Connects to the half−bridge output

Hgd

High−side driver

Drives the high−side half−bridge MOSFET

Boot

High side driver supply line

This pin supplies the internal high−side driver

SCY99080CDWR2G bảng dữ liệu(PDF) 3 Page - ON Semiconductor

SCY99080CDWR2G bảng dữ liệu(HTML) 3 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

bảng dữ liệu tải về

Link URL