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DP8500 bảng dữ liệu(PDF) 47 Page - National Semiconductor (TI) |
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DP8500 bảng dữ liệu(HTML) 47 Page - National Semiconductor (TI) |
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47 / 70 page ![]() 120 Dual Accessing Functions (DP8522A) (Continued) TLF9338 – B3 FIGURE 58b Wait States during a Port B Access 1232 LOCK Input When the LOCK input is asserted the currently granted port can ‘‘lock out’’ the other port through the insertion of wait states to that port’s access cycle LOCK does not disable refreshes it only keeps GRANTB in the same state even if the other port requests an access as shown in Figure 59 LOCK can be used by either port The user must guarantee that LOCK is not asserted with Port B granted when AVSRLRQ is asserted to request a VRAM transfer cycle 124 DUAL PORTING AND VRAM TRANSFER CYCLES The input AVSRLRQ disables any further internally or exter- nally requested refreshes or Port B access requests from being executed The AVSRLRQ input does this by making the VRAM controller arbitration logic think that a Port A ac- cess is in progress from the point where the AVSRLRQ in- put goes low until the VRAM shift register load operation is completed TLF9338 – B4 FIGURE 59 LOCK Function 47 |
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