ADP2450ASTZ-3-R7 datasheet(11/40 Pages) AD

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Data Sheet

ADP2450

Rev. B | Page 11 of 40

Pin No.

Mnemonic

Description

LFCSP

32-Lead

LQFP

48-Lead

GAIN0

Gain Setting for Programmable Gain Amplifier 1 to Amplifier 4. This pin is combined with

GAIN1 to set the gain of the amplifier.

RSTO

Reset Output (Open Drain). Connect this pin to a resistor to any pull-up voltage < 5.5 V.

FB2

Feedback Voltage Sense Input for Buck Regulator. Connect this pin to a resistor divider from

buck output voltage, VOUT2, for adjustable version. For the fixed output version, connect this

pin to VOUT2 directly.

PGND2

Power Ground for Buck Regulator.

Switch Node for Buck Regulator.

VIN

Power Input for Buck Regulator and Internal VREG. This voltage is monitored by the power

detection circuit. Connect a bypass capacitor between this pin and PGND2.

BST

Supply Rail for the Gate Drive of Buck. Place a 0.1 μF capacitor between SW and BST.

DET

Power Detection Output.

VPTH

Power Detection Voltage Threshold Setting. Connect a resistor between this pin and ground

to set the power rating detection voltage threshold.

FB1

Feedback Voltage Sense Input for boost shunt. Connect this pin to a resistor divider from VOUT1.

DRV

Boost Shunt Driver.

1, 5, 12, 14,

17, 20, 24, 25,

30, 31, 36, 37,

42, 46, 48

NIC

Not Internally Connected. Leave the pin open.

Exposed Pad. Solder the exposed pad to an external GND plane.

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