ADE1202 datasheet(26/42 Pages) AD

26 / 42 page

ADE1202

Data Sheet

Rev. 0 | Page 26 of 42

CHIP_

ADDR

ADDRESS

4 3 2

VALUE

CRC VALUE

SCLK

MOSI

MISO

Figure 43. SPI Read Operation with Appended Cyclic Redundancy Check (CRC)

CHIP_

ADDR

ADDRESS

4 3 2

SCLK

MOSI

Figure 44. SPI Broadcast Write Operation

Each time a register is written, the register value must be

verified by reading it back.

If multiple ADE1202 devices share the same SPI bus (as shown

in Figure 38) and the same register in multiple chips must be

initialized with an identical value, the broadcast write

functionality is available. Set Bit 15 in the SPI header word to 1

to enable a broadcast write, as shown in Figure 44. Bits[2:0]

(CHIP_ADDR) of the header word that indicate the chip

address on the SPI bus are ignored during a broadcast write.

SPI Read Operation

The registers of the ADE1202 can be read one at a time

following the protocol shown in Figure 42.

A read operation is initiated when the host controller sets the

CS pin low and begins sending a 16-bit command word (see

Figure 39). When the ADE1202 receives the last bit of the

header word, the device begins to transmit the register contents

on the MISO line when the next SCLK high to low transition

occurs. The host controller samples the data on the low to high

SCLK transition.

For an SPI read operation, Bit 3 of the command header must

be set to 1 (see Figure 39).

To ensure the integrity of the SPI read operation, a 16-bit CRC

(CRC-16) of the register value sent out on the MOSI pin can be

included in the transaction. If enabled, the ADE1202 appends

the CRC-16 value during the SPI read operation after the

If Bit 0 (SPI_CRC_APPEND_EN) in the CTRL register is

cleared to 0 (the default value), no CRC value is appended

during an SPI read operation. If the bit is set to 1, the CRC-16

value is appended to the register value read during the SPI read

operation.

The CRC algorithm is based on the standard CRC-16-CCITT

polynomial. The registers are introduced into a linear feedback

shift register (LFSR)-based generator one byte at a time, most

significant byte first, as shown in Figure 45. Each byte is then

used with the MSB first.

Figure 46 shows how the LFSR is used for CRC calculation. The

ADE1202 register forms Bits[a15:a0] used by the LFSR. Bit a0 is

Bit 15 of the register. Bit a15 is Bit 0 of the register.

LFSR GENERATOR

ADE1202

07 8

a15

Figure 45. CRC Calculation

LFSR

a15,a14,...a2,a1,a0

g15

b15

Figure 46. LFSR Generator Used for CRC Calculation

Bits bi(0) = 1, where i = 0, 1, 2, … 15, the initial state of the bits

that form the CRC. Bit b0 is the LSB, and Bit b15 is the MSB.

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