ADE1202 datasheet(39/42 Pages) AD

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Data Sheet

ADE1202

Rev. 0 | Page 39 of 42

ADC DECIMATED REGISTER

Address: 0x00F, Reset: 0x0000, Name: ADCDEC

Decimated ADC sample(s).

Table 33. Bit Descriptions for ADCDEC

Bits

Bit Name

Description

Reset

Access

[15:8]

ADCDEC2

ADC Channel 2 Decimated. The sample is decimated at the rate determined by the DECRATE bit field.

0x0

[7:0]

ADCDEC1

ADC Channel 1 Decimated. The sample is decimated at the rate determined by the DECRATE bit field.

0x0

PROGRAMMABLE LOAD CONTROL REGISTER

Address: 0x010, Reset: 0x0000, Name: PL_CTRL

Configures the programmable load into low idle mode or high idle mode.

Table 34. Bit Descriptions for PL_CTRL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

PL_MODE

Programmable Load Mode.

0x0

R/W

0: low idle state. In low idle state, the programmable load current is configured for PL_LOW_CODE when

the channel ADC code is greater than zero but less than the RISE_THR bit field. When the channel

ADC value rises above the PL_RISE_THR, the load current is set to PL_HIGH_CODE.

1: high idle state. In high idle state, the programmable load current is set to PL_HIGH_CODE when

the channel ADC code is higher than zero. The programmed load current flows as soon as there is

enough voltage headroom on the respective pin, the LOAD1 pin for Channel 1 or the LOAD2 pin

for Channel 2.

PROGRAMMABLE LOAD RISE THRESHOLD REGISTER

Address: 0x011, Reset: 0x001E, Name: PL_RISE_THR

Sets programmable load rising edge ADC sample threshold.

Table 35. Bit Descriptions for PL_RISE_THR

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x0

[7:0]

RISE_THR

Rising Edge Threshold. When configured in low idle mode, with PL_MODE = 0, when the ADC

value is greater than RISE_THR, the corresponding LOAD1 pin for Channel 1 or LOAD2 pin for

Channel 2) is configured to sink a high current (PL_HIGH_CODE).

0x1E

R/W

The minimum value that can be written is 0x01 and the maximum value is 0xFE. These values are

enforced by the hardware such that a write of 0x00 becomes 0x01 and 0xFF becomes 0xFE.

PROGRAMMABLE LOAD LOW CODE REGISTER

Address: 0x012, Reset: 0x001E, Name: PL_LOW_CODE

Programmable load low code.

Table 36. Bit Descriptions for PL_LOW_CODE

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

[5:0]

LOW_CODE

Programmable Load Low Code. Minimum low current value is in units of 100 µA. The minimum

value is 0x1. If 0x0 is written, LOW_CODE = 0x1.

0x1E

R/W

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