AD9161BBCZ datasheet(10/144 Pages) AD

10 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 10 of 144

DIGITAL INPUT DATA TIMING SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =

DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.

Table 7.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

LATENCY1

Interface

PCLK2 cycle

Interpolation

See Table 34

Power-Up Time

From DAC output off to enabled

DETERMINISTIC LATENCY

Fixed

PCLK2 cycles

Variable

PCLK2 cycles

SYSREF± to LOCAL MULTIFRAME

CLOCKS (LMFC) DELAY

DAC clock cycles

Total latency (or pipeline delay) through the device is calculated as follows:

Total Latency = Interface Latency + Fixed Latency + Variable Latency + Pipeline Delay

See Table 34 for examples of the pipeline delay per block.

PCLK is the internal processing clock for the AD9161/AD9162 and equals the lane rate ÷ 40.

JESD204B INTERFACE ELECTRICAL SPECIFICATIONS

VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 = DVDD_1P2 =

PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. VTT is the termination

voltage.

Table 8.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

JESD204B DATA INPUTS

Input Leakage Current

TA = 25°C

Logic High

Input level = 1.2 V ± 0.25 V,

VTT = 1.2 V

µA

Logic Low

Input level = 0 V

−4

µA

Unit Interval

1333

Common-Mode Voltage

VRCM

AC-coupled, VTT = VDD_1P21

−0.05

+1.85

Differential Voltage

R_VDIFF

110

1050

VTT Source Impedance

ZTT

At dc

Ω

Differential Impedance

ZRDIFF

At dc

100

120

Ω

Differential Return Loss

RLRDIF

Common-Mode Return Loss

RLRCM

SYSREF± INPUT

Differential Impedance

165-ball CSP_BGA (AD9162 only)

110

Ω

169-ball CSP_BGA

121

Ω

DIFFERENTIAL OUTPUTS (SYNCOUT±)2

Driving 100 Ω differential load

Output Differential Voltage

VOD

350

420

450

Output Offset Voltage

VOS

1.15

1.2

1.27

As measured on the input side of the ac coupling capacitor.

IEEE Standard 1596.3 LVDS compatible.

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